1. Field of the Invention
The present invention relates to lithographic technology of a method for fabricating a semiconductor device. In particular, the present invention relates to a method for evaluating a process margin of lithography.
2. Description of the Related Art
In order to evaluate a process margin of a lithographic process, it is necessary to obtain a highly accurate measurement of the dimensional dependency of a resist pattern on a light exposure and a focus position. With increasing fineness of a circuit pattern of a semiconductor device and increasing fineness of a resist pattern, the edge roughness of a resist and an error by a dimension measuring device are no longer negligible. If the dimension of the resist pattern cannot be measured with high accuracy, that is, if there are variations in dimension of the resist pattern, a process margin may not be accurately evaluated.
A light exposure and focus position have been assigned irrespective of the dimensional variations of the resist, followed by exposure. Thereafter, dimensions of the resist have been measured, and then, the process margin has been calculated. There have been few means for evaluating the reproducibility or error of the calculated process margin. Therefore, there has been an apprehension of overestimating or underestimating the process margin.